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Branch predictor
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#	Item
41	Illusionist: Transforming Lightweight Cores into Aggressive Cores on Demand Amin Ansari University of Illinois [removed] Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2013-01-25 16:46:06 Central processing unit Microprocessors Instruction set architectures Parallel computing DEC Alpha CPU cache Branch predictor Multithreading ARM architecture Computer architecture Computer hardware Computing
42	Alpha[removed]EV6 Microprocessor Hardware Reference Manual Order Number: DS–0027C–TE This manual is directly derived from the internal[removed]EV6 Specifications, Revision 4.5. You can access this hardware reference manu Add to Reading List Source URL: download.majix.org Language: English - Date: 2013-01-10 05:04:20 Computer engineering DEC Alpha PALcode Alpha 21264 CPU cache Branch predictor Processor register Instruction set Computer architecture Computer hardware Central processing unit
43	IEEE TRANSACTIONS ON DEPENDABLE AND SECURE COMPUTING (TDSC) 1 Using Register Lifetime Predictions to Protect Register Files Against Soft Errors Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2008-08-29 19:16:16 Central processing unit Computer memory Register renaming CPU cache Register file Branch predictor Parity bit Processor register 64-bit Computer architecture Computer hardware Computing
44	CAVA: Using Checkpoint-Assisted Value Prediction to Hide L2 Misses LUIS CEZE, KARIN STRAUSS, JAMES TUCK, and JOSEP TORRELLAS University of Illinois at Urbana–Champaign and JOSE RENAU Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-27 00:10:17 Central processing unit Computer memory Runahead Cache CPU cache Branch predictor Microarchitecture Memory hierarchy Speculative execution Computer architecture Computer hardware Computer engineering
45	Energy-Efficient Hybrid Wakeup Logic Michael Huang, Jose Renau, and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu ABSTRACT Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2002-07-31 19:49:18 Parallel computing Classes of computers Central processing unit Superscalar Branch predictor Reduced instruction set computing Instruction set Very long instruction word Microarchitecture Computer architecture Computing Computer hardware
46	CAP: Criticality Analysis for Power-Efficient Speculative Multithreading∗ James Tuck NC State University [removed] Wei Liu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2008-08-29 19:26:33 Technology Parallel computing Task parallelism Program Evaluation and Review Technique Branch predictor Central processing unit Flow network CREAM Graph theory Business Project management
47	ReSlice: Selective Re-Execution of Long-Retired Misspeculated Instructions Using Forward Slicing ∗ Smruti R. Sarangi, Wei Liu, Josep Torrellas, and Yuanyuan Zhou University of Illinois at Urbana-Champaign {sarangi,liuw Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2005-09-06 12:30:36 Computing CPU cache Data dependency Branch misprediction Branch predictor Instruction set Memory disambiguation Computer hardware Central processing unit Computer engineering
48	Using Register Lifetime Predictions to Protect Register Files Against Soft Errors∗ Pablo Montesinos, Wei Liu and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign {pmontesi, liuw Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2007-04-07 18:15:20 Central processing unit Computer memory Register renaming Register file CPU cache Branch predictor Parity bit 64-bit Processor register Computer hardware Computer architecture Computing
49	BlueShift: Designing Processors for Timing Speculation from the Ground Up∗ Brian Greskamp, Lu Wan, Ulya R. Karpuzcu, Jeffrey J. Cook, Josep Torrellas, Deming Chen, and Craig Zilles Departments of Computer Science and o Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2009-01-11 13:30:20 Electronic engineering Microprocessors Parallel computing Microarchitecture Intel Core Branch predictor Physical design CPU cache Static timing analysis Computer hardware Computer architecture Central processing unit
50	Flexible Snooping: Adaptive Forwarding and Filtering of Snoops in Embedded-Ring Multiprocessors∗ Karin Strauss Xiaowei Shen† Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2006-04-04 17:06:09 Cache coherency CPU cache Cache Central processing unit Computer memory MESI protocol Branch predictor Routing Snoop Dogg Computer architecture Computer hardware Computing

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